As memory chip capacities increase and the size of features used to form the memory cells decrease, defects in manufacturing become more of an impediment to produce memory chips with high yield. This is especially true for PROM memory chips, such as those that contain anti-fuse memory cells, which cannot be fully tested at manufacturing. Defects are most commonly either bad rows of cells, bad columns of cells, or bad individual cells. Many memory circuits include redundancy circuitry having special address decoding circuits that replace a row or column of memory cells when a defective cell is detected in initial testing of the chip. For example, redundancy circuitry can have non-volatile memory elements, such as polysilicon fuse elements, in decoder circuitry that are programmed in the factory to indicate the address of bad rows or columns. See, for example, “A 16 Mb Mask ROM with Programmable Redundancy,” Naruke et. al., ISSCC 89 THAM 10.1, Feb. 16, 1989, which describes spare rows and columns organized in a separate spare array and fuse elements to redirect addresses to the spare array. The fuses used to store the location or address of the bad lines can take-up a relatively large area in memories in which the area available for fuses is very limited.
While row redundancy can efficiently repair bad word lines and column redundancy can efficiently repair bad bit lines, neither efficiently repairs random bad cells. For example in page-oriented memory chips, a page contains all the information for 512 bytes of information. To simplify addressing when a row is replaced, all bits in the page are replaced. Accordingly, a single random bad cell repaired by row redundancy uses 4K redundant cells. Similarly, column redundancy uses many redundant cells to repair a single bad cell. In addition, using column redundancy to repair a single bad cell can be impractical in a page-oriented memory, as all previously-written pages in the portion or memory space defined by the bad column have to be moved to the redundant column.
Error correction code (ECC) can be used as an alternative method to improve memory yield and reliability. See, for example, “Circuit Technologies for 16 Mb DRAMs,” Mano et. al., ISSCC 87 WAM 1.6, Feb. 25, 1987. Hamming code, a commonly-used error correction code, adds 8 bits of information for each group of 64 bits of data, and the added information can be used to correct an error in the resulting 72-bit word. The added 8 bits of information can be generated by logic circuitry, such as a tree of exclusive-or gates. When the 72-bit word is read from memory, the logic circuitry decodes the 72-bit word to generate the 64 bits of data and can correct a single-bit error caused by a bad column or a random bad bit. Although Hamming code can correct single-bit errors, the improvement in memory yield and reliability comes at the price of storing an extra 8 bits for each group of 64 bits—a 12% overhead of additional cells. Additionally, single-bit correction may not be sufficient to provide good yield when there are both bad columns and random bad bits since the combination of a bad column and a random bad bit in a 72-bit word leads to an uncorrectable double-bit error.